Unsupervised Learning in Analog Networks

نویسندگان

  • Dean K. McNeill
  • Dave Blight
  • Chris Schneider
  • Bob McLeod
  • Zaifu Zhang
  • Martin Meier
  • Brion Dolenko
  • Brendan Frey
چکیده

ii I hereby declare that I am the sole author of this thesis. I authorize the University of Manitoba to lend this thesis to other institutions or individuals for the purpose of scholarly research. I further authorize the University of Manitoba to reproduce this thesis by photocopying or other means, in whole or in part, at the request of other institutions or individuals for the purpose of scholarly research. iii The University of Manitoba requires the signatures of all persons using or photocopying this thesis. Please sign below, and give address and date. Artificial neural networks have shown their usefulness in the solution of a number of complex problems such as pattern recognition and associative memories. Typically these networks are simulated on serial computers or using expensive vector processors. This thesis examines several issues important to the implementation of unsupervised learning algorithms in compact dedicated analog structures. Two unsupervised learning algorithms known as Coherence Based Unsupervised Learning (CBUL) and Competitive Learning are discussed in detail. A fully custom analog implementation of CBUL is presented and test circuitry implemented in 3 µ m CMOS is described. These circuits make extensive use of a CMOS version of the Gilbert multiplier to perform the majority of the neural computations. A complete implementation of the coherence based network , with capacitive weight storage, would consist of approximately 20 neu-rons and 400 synapses when fabricated on a 1cm silicon die in a typical 3 µ m technology. Additionally, the effect of inherent device fabrication variations are examined in terms of their effects on the construction of analog circuits for competitive learning. Several simulations are conducted involving a number of modelled hardware effects, including multiplier gain variations, errors due to noisy multipliers, multiplier zero-crossing offsets, and the effects of noisy input signals. These results demonstrate that competitive learning is tolerant of most expected fabrication variations with the exception of multiplier zero-crossing offset errors. ABSTRACT I would like express my thanks to my advisor Professor Howard Card, whose continual enthusiasm, wealth of inspirations, and direction were invaluable in the completion of this thesis. I would also like to thank my friends and colleagues who have been a valuable source of information and assistance throughout my graduate program. Most notably,net, a Network of Centres of Excellence, and was made possible with equipment loans and fabrication facilities provided through the Canadian Microelectronics Corporation.

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تاریخ انتشار 1993